This document describes the following:
- Description of the QDRII+/DDRII+ devices
- Differences between QDRII/DDRII and QDRII+/DDRII+ functionality and timing
- Design changes that need to be considered by system designers when migrating from QDRII/DDRII to QDRII+/DDRII+ devices
The table below outlines the differences between the QDRII/DDRII and QDRII+/DDRII+ SRAMs
Differences between QDRII / DDRII and QDRII+ / DDRII+
| QDR II / DDRII | QDRII+ / DDRII+ | Remark | |
|---|---|---|---|
| Frequency (PLL enabled)-65nm technology device |
120 MHz ~ 333 MHz |
120 MHz ~ 550 MHz |
Burst of 2 QDRII+/DDRII+ support 333 MHz and Burst of 4 QDRII+/DDRII+ support 550 MHz as highest frequency. |
| Organization | x8, x9, x18, x36 | x18, x36 | - |
| VDD | 1.8 V ± 0.1 V | 1.8 V ± 0.1 V | - |
| VDDQ | 1.8 V ± 0.1 V or 1.5 V ± 0.1 V | 1.8 V ± 0.1 V or 1.5 V ± 0.1 V | - |
| Read latency | 1.5 clocks | 2.0 & 2.5 clocks | QDRII+/DDRII+ read latency is not user selectable. Offered as two different devices. |
| Input clocks | Single ended (K,K#) | Single ended (K,K#) | - |
| Output clocks (C,C#) | Yes | No | - |
| ODT (On-Die Termination) | No | Offered in ODT and Non ODT versions | - |
| A0 (DDR B2) | Yes | No | - |
| A0, A1 (DDR B4) | Yes | No | - |
| Echo clock number | 1 Pair | 1 Pair | Echo clocks are single ended |
| PKG | 165 ball FBGA | 165 ball FBGA | - |
| Individual byte write (BW0#, BW1#) | Yes | Yes | - |