AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM

This application note explains the PowerSnoozeTM feature of Cypress’ 65-nm Asynchronous Fast SRAM devices (CY7S10xxG family). PowerSnooze allows the SRAM to enter into a low-power mode during long chip disable periods. A user-controlled pin (DS) allows seamless transition between high-speed mode and low-power mode. This application note also describes the critical timing parameters for the mode transitions as well as a sample SRAM interface configuration to use the PowerSnooze feature in application systems.