AN88889 - Mitigating Single-Event Upsets Using Cypress’s 65-nm Asynchronous SRAM

This application note introduces the Error Correcting Code (ECC) feature of Cypress’ 65-nm 16-Mbit Asynchronous SRAMs. It explains major causes of single-event upsets in systems and how they are mitigated conventionally. This application note also provides an overview of the ECC architecture implemented in Cypress’ 16M devices and explains the usage model for a new signal available in these devices that allows detecting single-bit upsets and their correction in Cypress’s SRAMs.