AN44517 gives the design recommendation for battery-backed SRAMs using a Cypress MoBL® SRAM (also called ultra low-power SRAM or micropower SRAM) and a microprocessor supervisory chip. This recommendation ensures better data integrity in SRAM, in case of power failures in a battery-backed application, when compared to other techniques that are also described in this document.
Battery Backed SRAM's (BBSRAM's), also called NVRAM's by system designers, are an important part of applications that require any kind of data backup in the event of a power failure. The block diagram below illustrates a simple FPGA/microcontroller-based application that contains a shared memory bus (Flash memory SRAM), a supervisor chip and a battery. In the event of a power failure, the battery-supervisor combination acts as a power backup for the SRAM, to ensure its contents are undisturbed. The supervisor chip places the SRAM in disable mode (standby) to reduce power consumption and extend battery life. This ensures data integrity and power savings.
The attached Application Note discusses Design Considerations that need to be taken into account when using Cypress MoBL SRAM's in these battery backed applications.
