This application note introduces the error correcting code (ECC) feature of Cypress’s 65-nm 16-Mb asynchronous SRAMs. It explains the major causes of single-event upsets in systems and how they are mitigated conventionally. This application note also provides an overview of the ECC architecture implemented in Cypress’s 16-Mb devices and explains the usage model of a new feature that detects and corrects single-bit upsets in Cypress’s SRAMs.
Introduction
Reliability and data integrity are two of the most important concerns of system designers with regard to memory devices. Modern systems cannot tolerate data corruption in memories due to environmental factors such as radiation. System designers have to rely on techniques such as off-chip error correction or redundancy to achieve higher reliability. These techniques result in overhead, in terms of either PCB space or additional processing time. Cypress’s latest generation of SRAMs offers a single-chip solution with on-chip error correcting code (ECC), reducing board space, cost, and design complexity. These SRAMs have high reliability (FIT rates of less than 0.1 FIT/Mb) compared to SRAMs without built-in ECC (FIT rate of greater than 150 FIT/Mb). This application note introduces a new feature of Cypress SRAMs that allows system designers to monitor error correction inside the SRAM.