Introduction
System cooling is a critical component of any high-power electronic system. As circuits become smaller, increasing demands are placed on system designers to improve the efficiency of system thermal management. This requires the system cooling fans to run at the optimum speed to ensure that the system temperature is always below a defined limit. To achieve this, a temperature measurement unit and a closed-loop fan speed controller are needed.
The temperature is measured based on the diode forward bias current dependence on temperature. This application note details how the flexible analog architecture of PSoC 3, PSoC 4, and PSoC 5LP enables you to measure diode temperatures using a single PSoC device.
The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:
|
Project |
Device
|
PSoC Creator
Version |
Development Kit
CY8CKIT-xxx |
Compiler
|
|||||||
|
Architecture
|
Silicon
Revision |
V3.0 CP7 or higher |
V2.2
|
001
DVK |
Keil
|
GCC
|
RVDS
|
MDK
|
|||
|
AN60590.zip |
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
|
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
Notes:
Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the most recent version of PSoC Creator:
The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
A variety of HID devices, including keyboard with LEDs and a composite device, are used as examples. This application note is a prerequisite for the advanced-level AN56377 and AN82072.
The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:
|
Project |
Device
|
PSoC Creator
Version |
Development Kit
CY8CKIT-xxx |
Compiler
|
|||||||
|
Architecture
|
Silicon
Revision |
V2.1 SP1 or higher |
V2.1/2.0
|
001
DVK |
Keil
|
GCC
|
RVDS
|
MDK
|
|||
|
AN58726.zip |
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
| AN58726_Archive.zip |
ES2, ES3, Prod
|
NO
|
YES
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
ES1
|
NO
|
YES
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:
The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
Power supervision plays a critical role in modern communications systems such as routers, switches, storage systems, servers and base stations. These systems require multiple power supply rails for their various components including ASICs, PHY devices, FPGAs, CPUs, memory modules, and peripheral I/O devices. Cypress’s PSoC® 3 Power Supervisor controls and monitors all of these rails and provides critical system functions:
.png) |
 |
| PSoC 3 Power Supervisor Block Diagram | PMBus Power Control Panel |
Video Series on PSoC® 3 Power Supervisor
This 4 part webisode series walks through the Power Supervisor solution running on PSoC 3 using the CY8CKIT-035 PSoC Power Management Expansion Board Kit (EBK). It’s a sneak preview of the application note AN76474.The series walks through each of the key IP building blocks that make up a full-featured Power Supervisor solution using PSoC.
PSoC Today! Power Supervisor Part I
PSoC Today! Power Supervisor Part II
PSoC Today! Power Supervisor Part III
PSoC Today! Power Supervisor Part IV
The following table provides the list of Devices and Development kits supported for this projects included in the application note:
|
Project |
Device |
Development Kit
CY8CKIT-xxx |
||||
|
Architecture |
Supported Device |
Silicon Revision
|
||||
|
PwrSpvr035_001.hex
|
CY8C3866AXI-040
|
ES3, Prod
|
YES
|
NO
|
YES
|
|
|
PwrSpvr035_030.hex
|
CY8C3866AXI-040
|
ES3, Prod
|
NO
|
YES
|
YES
|
|
|
PwrSpvr.hex
|
CY8C3666AXI-036
|
ES3, Prod
|
NA*
|
NA*
|
NA*
|
|
* Requires custom hardware. Refer to Application Note for details.
Introduction
The Cypress EZ-USB FX2LP (hereafter abbreviated as FX2LP) is a flexible USB 2.0 peripheral controller designed to handle maximum USB 2.0 bandwidth. To take full advantage of the USB 2.0 480 Mbps signaling rate, FX2LP contains specialized hardware to buffer the USB data and connect seamlessly to a variety of highbandwidth external devices such as MCUs, ASICs, and FPGAs. After a brief introduction to USB 2.0, this application note describes FX2LP features that contribute to its high throughput.
Cypress offers firmware development tools for its USB controllers such as EZ-USB® FX2LP™ and FX3™. These firmware tools allow you to develop USB devices at a high level because most of the low-level USB “plumbing” is already in place. In many cases, high-speed FX2LP and super-speed FX3 USB devices can be developed by modifying example Cypress firmware.
Cypress also provides software development tools for the host PC in the form of a Visual Studio .NET library. This library simplifies USB coding at the Windows level. This application note introduces the .NET class library and shows how to create a Windows example to send and retrieve data using a “bulkloop” firmware example running on an FX2LP or FX3 Development Kit (DVK).
Introduction
This application note demonstrates how to use the Cypress library for Microsoft .NET languages to implement host PC applications to communicate with Cypress's FX2LP and FX3 devices. Using this library, a Visual C#, Visual Basic, or Visual C++ program can communicate with an FX2LP or FX3-based device at a high level of abstraction.
The West Bridge® Antioch™ device is a USB and mass storage peripheral controller that is a perfect fit for handset applications. The baseband or applications processors in handset systems may need to use an integrated full-speed USB transceiver at times, and switch to the West Bridge Antioch device for high-speed USB operations. This requires the use of a USB switch. This application note discusses the implications of adding a USB switch with West Bridge Antioch and provides the PCB layout recommendations to avoid degradation of signal integrity.
You can also use this application note as a reference design guide to interface SPI F-RAM with other standard SPI master controllers. This application note includes an associated PSoC 4 example project.
Introduction
The SPI F-RAM is a serial nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory (F-RAM) is a nonvolatile RAM that eliminates the complexities, overhead, and system-level reliability problems caused by serial EEPROM and other nonvolatile memories. Unlike serial EEPROM and flash memories, the F-RAM performs write operations at bus speed without incurring any write delays (NoDelay™). Data is directly written into the memory array, and the next bus cycle can begin immediately without the need for data polling. The F-RAM products offer a very high endurance of 1014, orders of magnitude higher than serial EEPROM and flash memories.
Introduction
Today, the majority of automatic electronic controls for home appliance products use single-chip microcontrollers. Manufacturers develop real-time embedded firmware that executes in the MCU and provides hidden intelligence to control a home appliance. However, MCU damage caused by overheating, static discharge, or other factors can cause the appliance to enter an unknown or unsafe state.
The SPI nvSRAM is a slave SPI device and requires an SPI master controller to access nvSRAM in a system. This application note provides a few key design considerations and firmware tips to guide the users designing with SPI nvSRAM. An associated project for PSoC® 1 and a library component for PSoC 3 are also provided as an example project, which demonstrates SPI nvSRAM access by a standard SPI master controller.
Introduction
PSoC® 3 and PSoC 5LP devices provide tremendous power and flexibility for analog and digital applications, beyond what traditional MCUs offer. However, this flexibility raises new considerations when designing a PSoC device into a printed circuit board (PCB).
When designing a printed circuit board (PCB) for PSoC® 3 or PSoC 5LP, there are several considerations to keep in mind. These include proper connections for device power, reset, crystal, programming, and other pins. Good board layout techniques are also important, especially for precision analog applications. Finally, the PSoC 3 or PSoC 5LP device must be configured to work optimally in its hardware environment - the PSoC Creator™ IDE is used for this purpose.
This application note provides information on each of these topics, to help you to successfully design PSoC 3 or PSoC 5LP devices into a PCB and hardware environment.
Cypress Quad Data RateTM-II (QDRTM-II),QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for communication and data storage applications. The purpose of this application note is to assist designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.
(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)
Li-ion batteries are used in a wide range of systems such as cameras, cell phones, electric shavers, and toys. The charging circuit for the batteries can either be an integral part of the system (online charging) or an external plug-in circuit (offline charging). With its wide range of devices, PSoC offers a cost-effective solution in both segments. And with its configurable digital and analog features, PSoC 3 or PSoC 5LP enables implementation of other critical tasks required in the system.
|
Project |
Device
|
PSoC Creator
Version |
Development Kit
CY8CKIT-xxx |
Compiler
|
|||||||
|
Architecture
|
Silicon
Revision |
V3.0 or higher |
V2.1 SP1/
V2.1 |
001
DVK |
Keil
|
GCC
|
RVDS
|
MDK
|
|||
|
AN73468.zip |
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
| AN73468_Archive.zip |
ES3, Prod
|
NO
|
YES
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
ES1, Prod
|
NO
|
YES
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:
The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
The purpose of this application note is to provide a means to determine which architecture is right for a particular application. A brief description of each architecture and comparison by address/data relationships and performance characteristics is also included.
The table below shows the architecture comparison for the different options:
|
Parameter |
Std. Sync |
NoBLTM |
DDR-II/DDR-II+ |
QDRTM-II/ QDRTM-II+ |
|---|---|---|---|---|
|
Data Rate |
Single |
Single |
Double |
Double |
|
Data Bus |
Common I/O |
Common I/O |
Common and Separate I/O |
Separate I/O |
|
VDD |
3.3V/2.5V |
3.3V/2.5V |
1.8V |
1.8V |
|
VDDQ |
LVTTL 3.3V/2.5V |
LVTTL 3.3V/3.5V |
HSTL (1.5V/1.8V) |
HSTL (1.5V/1.8V) |
|
Clock Frequency |
250 MHz |
250 MHz |
333 MHz / 550 MHz |
333 MHz / 550 MHz |
Routines are developed and an application is shown to implement a µ-Law compressor that converts an analog voice band signal and produces a digitized 8-bit compressed value. An expanding DAC is also developed that restores the compressed digital value back to an analog value.
The DMA controller in PSoC® 3 and PSoC 5LP is used to handle data transfer without CPU intervention. This is useful in applications that require ADC data buffering and allows the CPU to do simultaneous tasks.
The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.
The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:
|
Project |
Device
|
PSoC Creator
Version |
Development Kit
CY8CKIT-xxx |
Compiler
|
|||||||
|
Architecture
|
Silicon
Revision |
V2.1 SP1 or higher |
V2.1/2.0
|
001
DVK |
Keil
|
GCC
|
RVDS
|
MDK
|
|||
|
AN61102.zip |
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
Prod
|
YES
|
NO
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
| AN61102_Archive.zip |
ES3, Prod
|
NO
|
YES
|
YES
|
YES*
|
NO
|
YES
|
N/A
|
N/A
|
N/A
|
|
|
ES1, Prod
|
NO
|
YES
|
YES
|
YES*
|
NO
|
N/A
|
YES
|
YES
|
YES
|
||
*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
Notes:
Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:
The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
Introduction
Cypress CY14E256LA is a 5 V, 256 Kbit (32 K x 8) nvSRAM in 0.13 micron technology. This part with a few performance enhancements is functionally equivalent to CY14E256L/STK14C88 in 0.8 micron technology but with a few differences in parameters. This application note highlights the differences between the CY14E256L/STK14C88 and the CY14E256LA and the parameters that must be considered while migrating.
Note STK14C88 is the Simtek part number for CY14E256L.
Introduction
Cypress CY14B256LA is a 3 V, 256 Kbit (32 K x 8) nvSRAM in 0.13 micron technology. This part with a few performance enhancements is functionally equivalent to STK14C88-3 in 0.8 micron technology but with a few differences in parameters. This application note highlights the differences between the STK14C88-3 and the CY14B256LA and the parameters of significance that must be considered while migrating.
